Reconfigurable Fast Fourier Transform Architecture for Orthogonal Frequency Division Multiplexing Systems

The performance of the Fast Fourier Transform computation plays a crucial role in the overall operation of OFDM modems. A VLSI architecture realizing the FFT has to perform in real time, adapt to various data rates and accommodate support for power dissipation requirements. This paper presents a VLSI architecture for real time FFT processing. The design involves four (4) radix-4 and one (1) radix-2 processing elements with complex multipliers and can be configured in real time to accommodate FFT computations of length 16, 32, 64, 128 and 256. For further speeding up the entire algorithm, the design can include a technique for parallel accessing the memory banks of each processing element. The validity and the efficiency of the architecture have been shown by an example implementation on FPGAs with throughput: each 256-length FFT at 2.48 usec.